
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   13:55:35 04/23/2012
-- Design Name:   mux_2to1
-- Module Name:   C:/Xilinx92i/mux/testbench_mux21.vhd
-- Project Name:  mux
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: mux_2to1
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY testbench_mux21_vhd IS
END testbench_mux21_vhd;

ARCHITECTURE behavior OF testbench_mux21_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT mux_2to1
	PORT(
		d0 : IN std_logic_vector(7 downto 0);
		d1 : IN std_logic_vector(7 downto 0);
		s : IN std_logic;          
		y : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL s :  std_logic := '0';
	SIGNAL d0 :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL d1 :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL y :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: mux_2to1 PORT MAP(
		d0 => d0,
		d1 => d1,
		s => s,
		y => y
	);



	tb : PROCESS
	BEGIN


		wait for 100 ns;
		d0 <= "00000000";
		d1 <= "11111111";
		s <= '0';
		wait for 100 ns;
		s <= '1';
		wait for 100 ns;
		s <= '0';
		wait for 100 ns;
		s <= '1';
		wait for 100 ns;
		s <= '0';
		wait for 100 ns;
		s <= '1';
		wait for 100 ns;
		s <= '0';
		wait; -- will wait forever
	END PROCESS;

END;
